This invention relates to a process for fabricating oxideisolated vertical bipolar transistors, complementary oxide-isolated lateral bipolar transistors, or composite bipolar transistors merging both a vertical and a lateral bipolar transistor and the resulting structures. In particular, the process and structures of the present invention relate to oxide-isolated vertical bipolar transistors, complementary lateral bipolar transistors or merged bipolar transistors whose operating characteristics may be optimized.
As a general objective it is desirable to be able to produce both vertical bipolar transistors and complementary lateral bipolar transistors using the same process steps. Vertical bipolar transistors, particularly vertical NPN's, are the most widely used device in bipolar integrated circuit design. The electron mobility in NPN's is greater than the hole mobility in PNP's. In such vertical bipolar transistors the base width can be accurately controlled and can be made as small as 0.1 micron by thermal diffusion or ion-implantation techniques. Thus, high device gain, B, can be achieved over a wide range of currents in small areas using controlled processing. When vertical bipolar transistors are used in the inverted mode, they are useful for common emitter/multi-collector structures which are frequently used in logic functions. Such structures can be realized by using a common buried layer as the emitter with separated collectors being formed in the surface of the epitaxial layer. This concept is disclosed in U.S. Pat. No. 3,244,950 issued to J. P. Ferguson. Lateral bipolar transistors, such as lateral PNP's, are highly useful for such applications as level shifters, active loads and current mirrors. See R. J. Widler, Journal of SolidState Circuits, Vol. SC-4, No. 4, August 1969. While it is within the state of the art to produce vertical bipolar transistors and complementary lateral bipolar transistors on the same chip, typically such joint fabrication requires that additional sequences of process steps be utilized in order to provide optimal versions of the two types of devices. It would be desirable, then, to be able to produce vertical bipolar transistors, i.e., vertical NPN's, and complementary lateral bipolar transistors, i.e., lateral PNP's, using the same process steps so that both types of devices can be incorporated on the same chip without additional process steps which usually lower yield and increase cost.
A new type of logic called integrated injection logic (also called merged transistor logic) has been proposed. It is a radically different but remarkably simple form of bipolar logic. Integrated injection logic (commonly abbreviated I.sup.2 L) reduces a gate to a complementary transistor pair. This complementary transistor pair may be integrated into a single device if the lateral device, e.g., lateral PNP, is used as the current source for the base of the vertical device, e.g., a vertical NPN, which is operating in an inverse mode. See Electronics, Feb. 21, 1974, pp. 92-95. See also Hart et al, "Bipolar LSI Takes New Direction with I.sup.2 L", Electronics, Oct. 3, 1974, pp. 111. The origin of this concept is found in two papers delivered to the IEEE International Solid-State Circuits Conference in February 1972. See H. H. Berger and S. K. Wiedman, "Merged Transistor Logic - a low-cost bipolar logic", Digest, 1972 ISSCC, pp. 90-91, Journal of Solid-State Circuits, Vol. 7, No. 5, October 1972, pp. 304-346, and C. J. Hart and A. Slob, "Integrated injection Logic - A New Approach to LSI", Digest, 1972 ISSCC, pp 92-93, Journal of Solid-State Circuits, October 1972, Vol. 7, No. 5, pp. 346-351. As described in these articles, integrated injection logic possesses the inherent advantage of being able to reduce the size of circuit elements since gates are reduced to a single device format, possesses an inherently low propagation-delay power product as a result of low operating voltage and capactance, and can generally be fabricated with as few as five masks. Using an additional masking step to form a buried layer associated with each silicon island, logic families such as T.sup.2 L, ECL and DTL may be fabricated on the same chip. Since each gate, as stated above, is comprised of a complementary transistor pair, it is desirable to be able to fabricate complementary transistor pairs, e.g., a vertical bipolar NPN and a complementary lateral PNP, using the same process steps and, since the complementary transistor pair may be integrated into the same device, it is especially desirable to be able to make a composite structure which incorporates a vertical bipolar transistor and a complementary lateral bipolar transistor.
Oxide-isolated devices are known to provide significant advantages over junction-isolated or cut-and-fill-isolated devices. The employment of Isoplanar oxide-isolation, as disclosed in U.S. Pat. No. 3,648,125 issued to Peltzer, particulaly in the walled emitter format (see W. D. Baker et al, "Oxide Isolation Brings High Density to Production Bipolar Memories", Electronics, March 29, 1973, pp. 67), accomplishes the objective of inter-device isolation, achieves high packing densities, reduces sidewall capacitances and reduces direct current losses for vertical bipolar devices. It would clearly be desirable, then, to be able to fabricate the merged complementary transistor pair described above utilizing oxide isolation. However, even though vertical bipolar transistors fabricated in the preferred walled emitter format have a considerably improved inverse gain, it is found that inversion of the base occurs between the emitter and collector along the oxide wall. This inversion occurs because charges in the oxide induce charges of opposite polarity at the silicon surface. For example, the charges due to Q.sub.ss and sodium ions are positive and induce a negative charge at the silicon surface. See Bruce E. Deal, "The Current Understanding of Charges in the Thermally Oxidized Silicon Structure", Journal of Electrochemical Society, Vol. 121, No. 6, June 1974, pp. 198C. In the case of a p-type silicon region, the presence of these charges depletes the p-type concentration and can invert the surface of the region to n-type. In addition, the p-type silicon is normally doped with boron which, during the oxidation process, preferentially segregates into the oxide and results in a lower concentration of boron at the surface than in the bulk silicon. To prevent this inversion, additional impurities of the same conductivity type as the base are introduced to the oxide wall adjacent the boundary with the base (see U.S. Pat. No. 3,648,125 issued to Peltzer; W. J. Evans et al, "Oxide-Isolated Monolithic Technology and Applications", Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973, pp. 373-379); these impurities are sometimes called field implants because they are implanted in the field oxide regions and are sometimes called guard rings because they guard the periphery of active regions from inversion. If the alternative of a more heavily doped base region is used, the beta of the vertical bipolar transistor is severely reduced because the beta (ratio of collector current to base current) is inversely related to the base impurity concentration; the result is that the use of a heavily doped base reduces the beta below normally acceptable values. The use of a p-type impurity in the oxide wall adjacent the boundary with the base, as stated above, can alleviate this problem, but since the base of the vertical bipolar transistor is also the collector of the lateral bipolar transistor and has the same conductivity type as the emitter of the complementary lateral bipolar transistor, the guard ring in the oxide wall tends to allow conduction between the emitter and collector of the lateral bipolar device, i.e., the solution to the inversion problem for the vertical bipolar transistor creates a new inversion problem for the lateral bipolar transistor, if one postulates a structure merging a lateral bipolar transistor and a complementary vertical bipolar transistor into a composite injection-logic gate.